[PDF] Random Forest Architectures on FPGA for Multiple Applications | Semantic Scholar (2024)

This paper presents an efficient architecture to perform random forest effectively for edge computing platforms based on Field Programmable Gate Array (FPGA) technology and proposes a sufficient structure for storing decision trees’ information for the execution of DTUs.

This work proposes a hierarchical memory layout suitable to the GPU/FPGA memory hierarchy, and designs three RF classification code variants based on that layout, and investigates GPU- and FPGA-specific considerations for these kernels.

This article proposes a flexible computing architecture consisting of multiple partially reconfigurable regions, pblocks, which each implement anomaly detectors, and compares fSEAD to an equivalent central processing unit (CPU) implementation using four standard datasets, with speedups ranging from 3× to 8×.

A hierarchical ensemble reduction and learning framework that bridges the gap between software-based ensemble methods and hardware computing in the IoT era and developed a novel conversion paradigm that supports the automatic deployment of >500 trees on a chip.

An FPGA design of an extremely low latency scientific machine learning application at the edge is presented and it is demonstrated that the implementation can achieve 60 nanoseconds of computing latency for complex random forest models with 10,000 input features.

Entree, the first automatic design flow for deploying the inference of Decision Tree (DT) ensembles over Field-Programmable Gate Arrays (FPGAs) at the network's edge, is proposed, which exploits dynamic partial reconfiguration on modern FPGA-enabled Systems-on-a-Chip (SoCs) to accelerate arbitrarily large DTEnsembles at a latency a hundred times stabler than software alternatives.

Due to their inherent structures, tree ensembles are ideal for exploiting the computational parallelism on FPGA, making them extremely potential for wearable devices and embedded systems at the edge nodes of the IoT.

The suitability of packet-level and flow-level features is validated using stepwise regression and random forest feature selection and it is indicated that random forest outperforms other algorithms achieving a maximum accuracy of 98.5% and an F-score of 0.932.

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A novel FPGA architecture for accelerating the RF training step is presented, exploring key features of the device and achieving speed-up factors up to 230x over a 3GHz Intel Core i5 processor when an Altera Stratix IV device is utilised under classification problems drawn from VOC2007.

FPGAs provide the highest performance solution, but require a multi-chip / multi-board system to execute even modest sized forests, while GP-GPUs offer a more flexible solution with reasonably high performance that scales with forest size, and multi-threading via Open MP on a shared memory system was the simplest solution.

Experimental results obtained on 23 datasets of standard University of California Irvine (UCI) Machine Learning Repository database suggest that the proposed architecture based on the sequence of universal nodes requires on average 56% less hardware resources compared with the previously proposed architectures, having the same throughput.

This paper identifies the compute-intensive kernel (Gini Score computation) in the algorithm, and develops a highly efficient architecture, which is further optimized by reordering the computations and by using a bitmapped data structure.

This work has devised a pipelined architecture for the implementation of axis parallel binary DTC that dramatically improves the execution time of the algorithm while consuming minimal resources in terms of area, and is 3.5 times faster than the existing hardware implementation of classification.

It is shown that the hybrid platform outperforms an optimised software implementation on an automotive grade ARM Cortex M4 processor in terms of latency and power consumption, also providing better consolidation.

Internal estimates monitor error, strength, and correlation and these are used to show the response to increasing the number of features used in the forest, and are also applicable to regression.

A novel incremental-learning algorithm, namely dynamic k-nearest-neighbor (DKNN), is developed to improve the accuracy of on-chip diagnosis, which employs online diagnosis data to update the learned classifier so that the classifier can keep evolving as new diagnosis data becomes available.

Some previous studies comparing ensemble methods are reviewed, and some new experiments are presented to uncover the reasons that Adaboost does not overfit rapidly.

A JTAG protection scheme, SLIC-J, is proposed to monitor user behavior and detect illegitimate accesses to the JTAG, which is characterized using a set of specifically-defined features, and then an on-chip classifier is used to predict whether the user is legitimate or not.

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